Electrically programmable fuses have been used extensively in the design and manufacture of Very Large Scale Integrated Circuits (VLSI).
Fuses are oftentimes used for redundancy purposes, wherein certain defective regions within an IC chip or a package can be electrically disconnected and replaced by a functional region. This technique of programming fuses has the advantage of increasing yield and adding flexibility to the circuit designer, and it is easily achieved by a "repair" or EC process well known to those skilled in the art.
In a typical circuit, a fuse may be incorporated in a predetermined region which can selectively be "blown" by applying a current through the fuse that generates sufficient joule heating to cause the fuse to melt, thereby rendering the line electrically isolated from other regions beyond the fuse location.
By way of example, Tsang in U.S. Pat. No. 3,792,319 describes a poly-crystalline silicon fusible link for Programmable Read Only Memories, wherein a doped fusible link is deposited on top of an insulating layer of an IC (Integrated Circuit) and is connected to the circuit through windows in the insulating and/or metallized layers. The fusible link may advantageously be protected by a layer that shields the fusible link and surrounding areas within the IC as well as providing means for minimizing heat transfer.
UK Patent No. 2,237,446A to Machida et al. describes a process wherein an opening is formed on the layers above the fuse region to efficiently dissipate the heat generated during the programming of the fuse. More particularly, all the layers on top of the regions either directly above or surrounding the fuse are removed to prevent damage and allow safe heat dissipation during programming by radiation to the environment. An illustration of this fuse structure is shown in FIG. 1.
Another typical fuse layout is described in Japanese Patent No 60-84838 to Yoshiharu Takeuchi and is illustrated in FIG. 2. Therein is shown a fuse that consists of several layers of thin dielectric films deposited on top of a conducting film made of doped poly-crystalline silicon. The fuse requires to be sufficiently thin to properly heat up during programming and must also be prone to become disabled at reasonable levels of current density. The heat generated during the programming process is considerable, and since many metals and Si melt at temperatures in excess of 1000.degree. C., the heat is dissipated to surrounding areas, usually causing damage such as cracked films, line breaks, destruction of organic layers, and the like.
Inherent to the fuse of the type described by Yoshiharu Takeuchi is a process of removing layers above the fuse with the intent of preventing heat damage to layers above the fuse. As such, Takeuchi uses the first layer of metal contact wiring to act as an etching stop layer when removing the layers above the fuse. Thus, the etch stop layer will be typically separated from the fuse layer by 1000-2000 .ANG. of a thin dielectric.
While the teachings of fuse formation and integration are well understood by those skilled in the art, fuses of the type previously described suffer from serious drawbacks.
Firstly, electrically programmable buried fuses create unwanted thermal damage. This is particularly true in an IC containing polyimide layers which are damaged by temperatures larger than 500.degree. C. Such temperatures easily can be reached while programming the fuse.
Secondly, prior art fuses dissipate energy at the expense of sacrificing the area above the fuse. Furthermore, at best only partial control on the amount of material to be removed above the fuse exists altogether. The lack of adequate control leaves the areas above the fuse totally unprotected and prone to extensive thermal damage during the programming phase. Clearly, this is a destructive method to all working areas in proximity of the fuse.
Thirdly, the etch stopping layer taught by Takeuchi is formed in the same plane as the contact metallurgy, which determines the layer thickness and proximity to the fuse and which prohibits any overlap of this etch stop layer with the contacts that could cause short circuits between the fuse contacts. Moreover, it also forces the fuse to be reprogrammed destructively at higher than typical power levels.
Fourthly, the voids left in the area above the fuse circuits in the prior art, lead to a non-planar surface, which is prone to capturing moisture or debris from subsequent handling. Additional masking steps and etching steps such as RIE (Reactive-Ion-Etch) is also required. The additional steps can potentially lead to lower yields and higher cost.
Lastly, the use of an aperture above the fuse to dissipate thermal energy during programming adds to the difficulties in scaling down the fuse dimensions for integration into the VLSI circuitry.